Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Sr Principal Design Engineer Location: Edinburgh, United Kingdom Reports to: Design Engineering Group Director Job Overview: The Cadence Silicon Solutions Group (SSG) develop leading edge Intellectual Property (IP) and Chiplet Solutions for a variety of High-Tech Markets. The Cadence IP & Chiplet solutions allow our Customers to tackle Silicon product development in a system context, enabling them to focus on product differentiation and to reduce time to volume. The Cadence Vision is to deliver industry leading IP & Chiplet solutions to enable our customers to be successful across fast-moving application spaces such as Physical AI, DataCentre and High Performance Computing. The Sr Principal Design Engineer will be based in Edinburgh as part of an experienced Front-End Engineering Team, working with our Global Chiplet team in Europe, India and the USA. Job Responsibilities: + Technical leadership of complex Silicon programs consisting of leading-edge IP + Work closely with our Chiplet Architecture team to define next generation Chiplets + Integration of Cadence IP Solutions e.g. UCIe, PCIe, Ethernet, USB, NPU, Audio, Vision + Integration of partner IP Solutions e.g. CPUs, ISP, Silicon Monitors, NoCs + Hands-on leadership of RTL, Testbench, Formal Analysis and Trial Synthesis activities + Quality Assurance, via implementation of hierarchical LINT, CDC and release flows + Planning of activities and milestones for Chiplet Subsystems and System IP development + Leadership of cross-functional technical meetings with domain leads e.g. Verification, SW + Support customer pre-sales and post-sales meetings + Participate in Technical Review Meetings and Checklist Reviews as part of ISO-9001 + Represent Cadence by presenting at Industry Conferences such as IEEE, DAC, CDNLive Job Qualifications: + Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline + 12+ years' experience in microelectronics/EDA industry + Experience of Verilog RTL Design essential + Experience of Metric Driven Verification (MDV) essential + Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis essential + Experience of SoC Architecture and Development essential + Experience of Technical Team leadership essential + Excellent oral and written English essential + Self-motivated with excellent planning, interpersonal, and communication skills Additional Skills/Preferences: + Experience of AMBA, PCIe, CXL & UCIe protocols preferred + Experience of Quality processes, such as ISO-9001 & ISO-26262 preferred Additional Information: Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace. Travel: <10% We're doing work that matters. Help us solve what others can't. Additional Jobs (https://cadence.wd1.myworkdayjobs.com/addl\_jobs) Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. + Read the policy(opens in a new tab) (https://www.cadence.com/content/dam/cadence-www/global/en\_US/documents/company/careers/equal-employment-opportunity-policy.pdf) We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact staffing@cadence.com. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (https://www.cadence.com/en\_US/home/privacy/privacy-policy.html) . E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (https://www.cadence.com/content/dam/cadence-www/global/en\_US/documents/company/careers/e-verify-participation-poster.pdf) Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. ? Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.